Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder

We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, Serviceability (RAS) of high performance microprocessors, by specifically targeting one of its most critical blocks (from the point of view of the microprocessor RAS), that is the control logic. By discovering codes that are inherently present within the control logic because of its performed functionality and verification needs (referred to as Control Logic Function-Inherent Codes), it allows to achieve concurrent error detection at very limited costs in terms of area, power consumption, impact on performance and design. Considering for instance the case of the instruction decoder of a public domain microprocessor, we will prove that our approach requires significantly lower area and power than traditional parity encoding, while providing higher concurrent error detection ability. Therefore, if adopted together with a system level (generally software implemented) recovery technique, our strategy constitutes a viable and successful approach to increase the microprocessor RAS, at very limited costs